This paper presents a folding and interpolating ADC in a 0.13−/μm CMOS technology, which achieves 10−bit resolution and 200−MS/s sample rate despite the limitations of a 1.2V supply voltage. The converter employs an open-loop auto-zero technique to cancel preamplifier offsets, and preamplifiers provide sufficient gain to overcome offsets from the following stages, which enable 8.6 ENOB (53.5 dB SNDR) to be reached. The IC measures 3.24 mm² including pads and consumes 195mW in total.