This paper presents a multiword based error correction code (MECC) scheme to mitigate SEUs in low-voltage SRAMs. MECC combines four 32 bit data words to form a composite 128 bit ECC word and uses optimized transmission-gate XOR logic, thus significantly reducing check-bit overhead and error correction time, respectively. Use of composite word warrants a unique write operation where MECC updates checkbits by simultaneously writing one data word and reading the other three data words. Two composite words are interleaved in a row to tackle multi-bit SEU. In addition, the supply voltage of the SRAM is reduced to save leakage and active power. A 64kb SRAM with MECC implemented in 90nm CMOS technology consumes 154 muW leakage power and 375 muW active power at 0.6 V and 100 MHz, showing improved area and speed-power efficiency than conventional single-word ECC and existing multiword ECC schemes.