Abstract:
This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power ...Show MoreMetadata
Abstract:
This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.
Published in: 2011 Proceedings of the ESSCIRC (ESSCIRC)
Date of Conference: 12-16 September 2011
Date Added to IEEE Xplore: 13 October 2011
ISBN Information: