Abstract:
This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle eac...Show MoreMetadata
Abstract:
This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning. The chip was used as part of a ADC/DSP/DAC chain which, unlike the case with conventional, clocked systems, maintains its frequency response intact when the sample rate changes. For certain inputs, the system has signal-to-error ratio which exceeds that of clocked systems.
Published in: 2013 Proceedings of the ESSCIRC (ESSCIRC)
Date of Conference: 16-20 September 2013
Date Added to IEEE Xplore: 31 October 2013
ISBN Information:
Print ISSN: 1930-8833