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A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis | IEEE Conference Publication | IEEE Xplore

A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis

Publisher: IEEE

Abstract:

This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achiev...View more

Abstract:

This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm 2 . The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.
Date of Conference: 16-20 September 2013
Date Added to IEEE Xplore: 31 October 2013
ISBN Information:
Print ISSN: 1930-8833
Publisher: IEEE
Conference Location: Bucharest, Romania

References

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