A power-efficient 2.4 GS/s 10-bit time-interleaved SAR ADC is presented. To reduce the power consumption, several conversion cycles are skipped as the input signal falls within a predefined bypass window. To enhance the operation speed, two alternate comparators are adopted in each ADC channel. The comparator offset is calibrated only when the bit bypass is triggered. This eliminates the need of a dedicated calibration cycle and the conversion rate degradation is avoided. The reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without introduction of power-hungry distributed reference buffers. Fabricated in a 28 nm FDSOI process, the proposed ADC achieves 49.02 dB SNDR and a Nyquist Walden FOM of 17.7 fJ/conv.-step at 2.4 GS/s.