A compact analytical model is reported capturing the effects of Coulomb Blockade and charge quantization on the drain current characteristics of a MOSFET-based semiconductor quantum dot at cryogenic temperatures. It is implemented as a Verilog-A add-on to the foundry-provided MOSFET model to facilitate potential integration in any design kit and allow for simulation of quantum processors that integrate qubits and control electronics on the same die. The model was verified in the 6-50 K temperature range on the measured I-V characteristics of a nanoscale p-MOSFET fabricated in production 22nm FDSOI CMOS technology.