This work presents a scalable bit-serial computing hardware accelerator for solving two/three-dimensional (2D/3D) partial differential equations (PDEs). The finite difference method (FDM) approximates the PDEs by solving algebraic equations that contain finite differences between discretized solutions in a 2D/3D grid. The proposed PDE solving hardware accelerator comprises a $\mathbf{16}\times\mathbf{16}$ regular PE array, where neighboring PEs are connected based on a 2D lattice graph configuration. The regular PEs update their solutions corresponding to a 2D/3D grid based on serial bit-streams coming from their neighboring PEs. Besides the regular PEs, $\mathbf{4}\times\mathbf{16}$ boundary PEs surrounding the regular PEs store and transmit boundary conditions to the regular PEs adjacent to them. The proposed PDE solver with distributed 92Kb embedded SRAM can be reconfigured to map and solve 2D/3D Laplace and Poisson equations using a sequential layer-by-layer update method with no external memory access. A fabricated 65nm test chip occupying the core area of 0.811mm² consumes 5.2pJ and 6.5pJ, respectively, when solving 2D and 3D PDEs at 1V and 25.6MHz.