Abstract:
Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN...Show MoreMetadata
Abstract:
Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN bi-layers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improved by using low temperature solid-phase epitaxial re-growth process in combination with the Smart Cut™ technology. An original process integration scheme is described in order to minimize the diode leakage.
Date of Conference: 16-20 September 2013
Date Added to IEEE Xplore: 22 May 2014
Electronic ISBN:978-1-4799-0649-9