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Identifying failure mechanisms in LDMOS transistors by analytical stability analysis | IEEE Conference Publication | IEEE Xplore

Identifying failure mechanisms in LDMOS transistors by analytical stability analysis


Abstract:

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure ...Show More

Abstract:

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.
Date of Conference: 22-26 September 2014
Date Added to IEEE Xplore: 06 November 2014
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Conference Location: Venice Lido, Italy

References

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