A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design | IEEE Conference Publication | IEEE Xplore

A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design


Abstract:

In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Star...Show More

Abstract:

In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices. The model accounts for the intrinsic randomness in the number of defects contributing to the RTN and their properties. Moreover, it can be readily integrated in existing RRAM device compact models, extending their capabilities. The model is implemented in Verilog-A, and its effectiveness is demonstrated by using it to design the building block of a Truly-Random Number Generator circuit exploiting the RTN randomness as an entropy source.
Date of Conference: 11-14 September 2017
Date Added to IEEE Xplore: 16 October 2017
ISBN Information:
Electronic ISSN: 2378-6558
Conference Location: Leuven, Belgium

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References

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