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Back-end-of-line CMOS-compatible diode fabrication with pure boron deposition down to 50 °C | IEEE Conference Publication | IEEE Xplore

Back-end-of-line CMOS-compatible diode fabrication with pure boron deposition down to 50 °C


Abstract:

Pure boron deposited on silicon for the formation of p+n-like junctions was studied for deposition temperatures down to 50 °C. The commonly used chemical-vapor deposition...Show More

Abstract:

Pure boron deposited on silicon for the formation of p+n-like junctions was studied for deposition temperatures down to 50 °C. The commonly used chemical-vapor deposition method was compared to molecular beam epitaxy with respect to the electrical characteristics and the boron-layer compactness as evaluated by etch tests, ellipsometry and atomic force microscopy. Electrically, the important parameters are minority carrier electron injection into the p-type region and the sheet resistance along the boron-to-silicon interface which appear to be independent of deposition method for temperatures down to 300 °C. Only with molecular beam epitaxy did we succeed in producing substantial layers for the lower temperatures down to 50 °C. Also, at this very low temperature, p+n-like diodes were formed, but the suppression of electron injection was less efficient than at the higher temperatures. From simulations, assuming that the attractive electrical behavior is due to a monolayer of fixed negative charge at the interface, the concentration of holes needed to explain the I-V characteristics is estimated to be 1.4×1011 cm-2 for 50 °C deposition and 1.1×1013 cm-2 for 400 °C.
Date of Conference: 23-26 September 2019
Date Added to IEEE Xplore: 18 November 2019
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Conference Location: Cracow, Poland

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