In this work, a reconfigurable one FeFET-one RRAM (1FeFET1R) design was proposed to realize multiple logic gate functions. A TCAD FeFET device model with parameters calibrated with the fabricated device data and a 1FeFET1R circuit model based on it were developed. 16 types of logic gate operations were demonstrated with the 1FeFET1R structure and the cascade logic circuits. By simulation, the relationship of RRAM resistance and the output voltage window at different supply voltage Vdd for various logic gates is investigated. The output window based on current FeFET and RRAM technology can be greater than 0.5Vdd for Vdd = 1.2 V/1.5 V. Overall, the proposed 1FeFET1R structure is feasible, area efficient and simple in design, which can be possibly adopted in the future logic-in-memory architectures.