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Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs | IEEE Conference Publication | IEEE Xplore
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Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs


Abstract:

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the...Show More

Abstract:

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.
Date of Conference: 28-31 May 2012
Date Added to IEEE Xplore: 09 July 2012
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Conference Location: Annecy, France

References

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