Nanometric scaling steadily increases failure rates, which are expected to be exacerbated as we are approaching the ultimate limits of CMOS and to worsen yet as we will engage in post-CMOS technologies. Moving towards ultimate CMOS and post CMOS also requires increasingly aggressive power reduction. An efficient way to reduce power consists in reducing voltage. Aggressive voltage reduction will result in increasing the numbers of weak memory cells that will operate falsely. Thus, it is desirable to dispose memory repair architectures able to cope with high defect densities. At the same time, reliability is another major concern with aggressive technology scaling. In this context, recent techniques combining memory repair architectures with ECC were able to aggressively reduce repair cost for high defect densities. However, even under the drastic cost reduction obtained with these approaches, power penalty can still be significant as we consider increasing levels of defect density. This paper proposes new repair architectures that are advantageously combined with the previously proposed solutions and allow drastic reduction of dissipated power.