Abstract:
The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we prop...View moreMetadata
Abstract:
The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we propose a technique for irredundant description of FSM models of parallel-pipeline designs. The technique allows to implicitly specify complex compositional FSM models and to automate construction of test sequences by composing several parallel operations into multi-stimuli.
Published in: 2010 East-West Design & Test Symposium (EWDTS)
Date of Conference: 17-20 September 2010
Date Added to IEEE Xplore: 05 April 2011
ISBN Information: