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Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models | IEEE Conference Publication | IEEE Xplore

Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models

Publisher: IEEE

Abstract:

The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we prop...View more

Abstract:

The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we propose a technique for irredundant description of FSM models of parallel-pipeline designs. The technique allows to implicitly specify complex compositional FSM models and to automate construction of test sequences by composing several parallel operations into multi-stimuli.
Date of Conference: 17-20 September 2010
Date Added to IEEE Xplore: 05 April 2011
ISBN Information:
Publisher: IEEE
Conference Location: St. Petersburg, Russia

References

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