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A design for testability technique for quantum reversible circuits | IEEE Conference Publication | IEEE Xplore

A design for testability technique for quantum reversible circuits


Abstract:

This paper shows that in a (n×n) reversible circuit implemented with k-CNOT gates, addition of only two extra input lines along with insertion of few k-CNOT gates can yie...Show More

Abstract:

This paper shows that in a (n×n) reversible circuit implemented with k-CNOT gates, addition of only two extra input lines along with insertion of few k-CNOT gates can yield an easily testable design, which admits a universal test set of size (n+1) to detect all SMGFs, PMGFs, and detectable RGFs in the circuit.
Date of Conference: 27-30 September 2013
Date Added to IEEE Xplore: 25 November 2013
ISBN Information:
Conference Location: Rostov on Don, Russia

References

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