Rapidly developing FinFET technology, alternative to the conventional planar technology, plays an important role in routing modern silicon industry. Due to unique structure of FinFET transistors the defect types and resulting fault models is different for FinFET transistors compared to planar ones. As a result the well-established flow used for embedded test and repair solutions development for MOSFET-based memories fails to be smoothly deployed for FinFET-based memories as well. Thus there is a need to modify the existing solution to support FinFET-based memories. In the scope of this paper the upgraded test methodology flow is introduced for FinFET-based memories, as well as the high-level overview of the comprehensive study is presented which was conducted using the described flow.