Abstract:
Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test pa...Show MoreMetadata
Abstract:
Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.
Published in: 2016 IEEE East-West Design & Test Symposium (EWDTS)
Date of Conference: 14-17 October 2016
Date Added to IEEE Xplore: 09 January 2017
ISBN Information:
Electronic ISSN: 2472-761X