Abstract:
Nowadays electronic systems are moving toward more complex designs with various computation and communication blocks. In addition to test requirements for individual syst...Show MoreMetadata
Abstract:
Nowadays electronic systems are moving toward more complex designs with various computation and communication blocks. In addition to test requirements for individual system blocks, the functionality of the overall system must also be tested. Conventional test methods cannot satisfy this requirement due to their limited scope, and time and cost constraints. For this purpose, the concept of system-level test (SLT)has gained attention. However, there are different views on SLT in the literature. Some works consider board-level testing of a complete system as SLT, and others propose system-level fault models, test generation, and design-for-testability for analog, digital, communications, and software parts of a system. Our proposal is a SystemC-based integrated test platform for the SLT model. This model must anticipate the behavior of the system and the effects of different components on each other. Furthermore, it can observe faults on not only the outputs but also intermediate signals of the system.
Published in: 2019 IEEE East-West Design & Test Symposium (EWDTS)
Date of Conference: 13-16 September 2019
Date Added to IEEE Xplore: 30 October 2019
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