Large-scale packet queueing and scheduling is the basis for today’s Quality of Service (QoS) in computer access networks, especially to achieve guaranteed high throughput and low latency. While highly performant fixed-function ASICs offer sufficient functionality for most data center use-cases, as of today, they cannot support all functionality required for access networks, e.g., QoS-aware packet queueing.In this poster, we present an FPGA-based architecture for network packet queueing optimized for residential and mobile Internet access networks.