In this paper we present an implementation of the image compression routine SPIHT in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an ASIC, is provided along with background material on the image compression algorithm. We analyzed several discrete wavelet transform architectures and selected the folded DWT design. In addition we provide a study on what storage elements are required for each wavelet coefficient. The paper uses a modification to the original SPIHT algorithm needed to parallelize the computation. The architecture of the SPIHT engine is based upon fixed-order SPIHT, developed specifically for use within adaptive hardware. For an N /spl times/ N image fixed-order SPIHT may be calculated in N/sup 2//4 cycles. Square images which are powers of 2 up to 1024 /spl times/ 1024 are supported by the architecture. Our system was developed on an Annapolis Microsystems WildStar board populated with Xilinx Virtex-E parts.