The finite radon transform (FRAT) is a fundamental block of the curvelet and ridgelet transforms, both of which were recently introduced to overcome the limitations of wavelets. In this paper, two novel high speed/low power VLSI architectures for the FRAT are presented. Both are serial input architectures and have a time complexity of O(p/sup 2/(p+1)) and O(p/sup 2/) respectively, where p is the block size. The first architecture is fully scaleable, while the second architecture is further optimised for high throughput and low power. Both architectures are implemented on the Virtex FPGA series, and prototyped on the Celoxica RC1000 development board.