Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation | IEEE Conference Publication | IEEE Xplore

Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation


Abstract:

The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpo...Show More

Abstract:

The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.
Date of Conference: 27-29 August 2007
Date Added to IEEE Xplore: 12 November 2007
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Conference Location: Amsterdam, Netherlands

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