A Design Flow to Map Parallel Applications onto FPGAs | IEEE Conference Publication | IEEE Xplore

A Design Flow to Map Parallel Applications onto FPGAs


Abstract:

This paper introduces a new flow able to fit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based ...Show More

Abstract:

This paper introduces a new flow able to fit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the application. Significant experiments have validated the approach.
Date of Conference: 27-29 August 2007
Date Added to IEEE Xplore: 12 November 2007
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Conference Location: Amsterdam, Netherlands

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