An FPGA Based Memory Efficient Shared Buffer Implementation | IEEE Conference Publication | IEEE Xplore
Subscribe
ADVANCED SEARCH
Conferences >2007 International Conference...

An FPGA Based Memory Efficient Shared Buffer Implementation

PDF
Dwayne Burns; Ciaran Toal; Kieran McLaughlin; Sakir Sezer; Mike Hutton; Kevin Cackovic
All Authors

Abstract:

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs...Show More

Metadata

Abstract:

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
Published in: 2007 International Conference on Field Programmable Logic and Applications
Date of Conference: 27-29 August 2007
Date Added to IEEE Xplore: 12 November 2007
ISBN Information:

ISSN Information:

DOI: 10.1109/FPL.2007.4380740
Conference Location: Amsterdam, Netherlands
Contents
Contact IEEE to Subscribe

References

References is not available for this document.

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.