DWARV: Delftworkbench Automated Reconfigurable VHDL Generator | IEEE Conference Publication | IEEE Xplore

DWARV: Delftworkbench Automated Reconfigurable VHDL Generator


Abstract:

In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation paralleli...Show More

Abstract:

In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.
Date of Conference: 27-29 August 2007
Date Added to IEEE Xplore: 12 November 2007
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Conference Location: Amsterdam, Netherlands

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