This paper describes the architecture and design flow of a self-reconfigurable embedded system, mapped on a Spartan-3 low-cost FPGA, where a fixed area is reserved to accommodate a reconfigurable coprocessor. Spartan-3 low-cost family lacks of the ICAP (Internal Configuration Access Port) and design tools for self-reconfiguration. The paper also deals with other issues, such as OPB isolation, bit-stream retrieve from external SRAM, bit-stream processing, and clock routing.