Loading [a11y]/accessibility-menu.js
In pursuit of instant gratification for FPGA design | IEEE Conference Publication | IEEE Xplore

In pursuit of instant gratification for FPGA design


Abstract:

This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of precompiled mo...Show More

Abstract:

This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of precompiled modules and associated meta-data, bitstream-level assembly of desired designs can occur in a fraction of the time of traditional back-end tools. Modules are bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. Since vendor tools are not needed for assembly, compilation can be performed in embedded and/or untethered environments. As a result, large device compilations can be assembled in seconds. This turbo flow (TFlow) enables software-like turn-around time for faster prototyping and increased productivity.
Date of Conference: 02-04 September 2013
Date Added to IEEE Xplore: 24 October 2013
Electronic ISBN:978-1-4799-0004-6

ISSN Information:

Conference Location: Porto, Portugal

References

References is not available for this document.