Abstract:
Packet classification requires multiple fields of the packet header to be matched against entries in a prioritized table; it is still challenging to support dynamic updat...Show MoreMetadata
Abstract:
Packet classification requires multiple fields of the packet header to be matched against entries in a prioritized table; it is still challenging to support dynamic updates for packet classification without sacrificing throughput performance. In this paper, we present a high-throughput pipelined architecture for packet classification on FPGA supporting dynamic updates of the rule set. This architecture is based on Dynamic Bit Vector (Dynamic-BV) approach and supports modify, delete and insert operations during run-time with very little impact on sustained throughput. Experimental results show that, for a 1K rule set on a state-of-the-art FPGA, a throughput of 120 Gbps with 1 million updates/second can be sustained using a single pipeline.
Date of Conference: 02-04 September 2013
Date Added to IEEE Xplore: 24 October 2013
Electronic ISBN:978-1-4799-0004-6