This paper proposes a new architecture for the implementation of multiplier-less FIR digital filters with programmable sum-of-powers-of-two (SOPOT) or canonical signed digit (CSD) coefficient representations. The multiplier-less FIR filter is implemented as the direct form structure with the filter coefficients represented as SOPOT representation, which can be realized as limited number of shifts and additions. Traditional VLSI implementations of multiplier-less FIR filters are usually hardwired and the filter coefficients cannot be programmed online. The proposed architecture is very modular in the structure and it can be connected to implement the multiplier-less FIR filter with arbitrary filter order and SOPOT terms using programmable SOPOT coefficients. The structure is also pipelined to achieve a high data throughput rate at low hardware cost. The proposed architecture was implemented and tested using the Altera FLEX 10K Field Programmable Gate Arrays (FPGA). The finite wordlength effect such as signal roundoff and overflow errors are also taken into account. A design example is given to demonstrate the feasibility of the proposed architecture.