A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and "hides" the cost of reconfiguration by exploiting vertical integration. Each cell in the array can act as logic or interconnect, or both - contrasting with current FPGA structures in which logic and interconnect are built and configured largely as separate items. Simulation results for a SOI DG-MOSFET implementation is presented and two alternative non-silicon device technologies, metal-insulator-metal and carbon nanotube transistors, are briefly explored Of these, carbon nanotube devices appear to offer the highest current drive at the limit of scaling and will operate into the gigahertz range but then only within architectures that are locally connected.