In this work a new FPGA based hardware accelerator (gNBX) for self-organizing maps is introduced. New principles for hardware acceleration of self-organizing maps, which increase the degree of parallelity and therefore the acceleration gain was presented. Our technology independent design description can be mapped on application specific integrated circuits if very high performance is required, as well as on field programmable gate arrays (FPGAs), which offer mid level performance (a speed up factor of up to 70 in comparison with PCs for typical datasets is achieved) at relatively low costs. Additionally, FPGAs offer the flexibility to adapt the hardware to the changing requirements of the application during runtime. Therefore, the hardware can be exploited optimally at all times during the simulation process. Several benchmark scenarios with well known datasets shows the performance of our system.