Abstract:
This work explores the reconfigurable dataflow approach in producing efficient hardware pipelines for programs with loop-carry dependencies in nested loops. Reconfigurabl...Show MoreMetadata
Abstract:
This work explores the reconfigurable dataflow approach in producing efficient hardware pipelines for programs with loop-carry dependencies in nested loops. Reconfigurable dataflow combines static and dynamic scheduling, and employs tagged tokens to enable reassembling of results which can retire out of order. The effectiveness of this approach is illustrated using a fractal set generator and a Newton-Raphson root polisher: implementations targeting Xilinx Virtex and Virtex-II FPGAs can run up to 55 times faster than hardware pipelines developed using other methods, at the expense of a 50% increase in area.
Published in: Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
Date of Conference: 06-08 December 2004
Date Added to IEEE Xplore: 14 February 2005
Print ISBN:0-7803-8651-5