Co-simulation is one of the most efficient verification techniques for embedded systems. For the case of FPGAs there are no available tools for CSoCs using soft processors. Only in the case of hard processors the same tools, originally developed for ASIC designs, can be used. This work presents an efficient and modular co-simulation framework for soft processors. Increased efficiency is obtained using a compiled instruction set simulator. Additional co-simulation speed improvement is achieved by tightly coupling the framework to the development environment.