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Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers | IEEE Conference Publication | IEEE Xplore

Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers


Abstract:

We propose the use of laterally graded channel doping and High-K Spacers positioned on both sides of gate oxide to improve the Performance and thereby, the scalability of...Show More

Abstract:

We propose the use of laterally graded channel doping and High-K Spacers positioned on both sides of gate oxide to improve the Performance and thereby, the scalability of Junctionless Nanowire Field Effect Transistors (JLNWFET). The performance parameters of the device considered in this study are ION/IOFF ratio, Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Slope (SS). Using extensive 3-D TCAD simulations, we have analyzed that the OFF-state leakage, DIBL and SS can be reduced owing to the combined use of laterally graded-doping channel and High-k Spacers.
Date of Conference: 27-30 October 2015
Date Added to IEEE Xplore: 04 February 2016
ISBN Information:
Conference Location: Osaka, Japan

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