SystemVerilog behavior models of power converter integrated circuits for mixed-level design methodology was proposed. When SystemVerilog is used to establish behavior models for circuits, the process of transistor-level design can be omitted to prevent prolonging the redesign time. Moreover, models created in this manner can sustain simulation accuracy while reducing the simulation time by 57% compared with models conventionally created using Verilog-AMS. In this study, 0.18-μm CMOS fabrication was used to verify the effectiveness of the proposed SystemVerilog model and mixed-level design in the creation of a digitally controlled buck converter integrated circuit.