Abstract:
This paper introduces a new parallel carrier recovery architecture suitable for ultra- high speed intradyne coherent optical receivers (e.g., ≥40Gb/s). The proposed schem...Show MoreMetadata
Abstract:
This paper introduces a new parallel carrier recovery architecture suitable for ultra- high speed intradyne coherent optical receivers (e.g., ≥40Gb/s). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only frequency offset, but also frequency fluctuations such as those induced by mechanical vibrations. It is well-known that nonzero frequency offset leads to higher phase error variance in a feedforward CPR. Furthermore, it has been recently shown that laser frequency instability caused by mechanical vibrations significantly degrades the performance of CPR. Other effects such as power supply noise may also introduce laser frequency fluctuations. To avoid receiver performance degradations, both frequency offset and frequency fluctuations should be compensated before the feedforward CPR block. We show that this task can be achieved by using a typical decision-directed serial DPLL. Then, a new approximation to the DPLL computation is introduced to enable a parallel-processing implementation in multigigabit per second receivers. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while providing a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed parallel carrier recovery architecture.
Date of Conference: 05-09 December 2011
Date Added to IEEE Xplore: 19 January 2012
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