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Intel’s Post Silicon functional validation approach | IEEE Conference Publication | IEEE Xplore

Intel’s Post Silicon functional validation approach


Abstract:

CPU Post-Silicon functional validation is the last "guardian" logic-wise before delivering the product to the market. In each CPU generation, the challenges are larger du...Show More

Abstract:

CPU Post-Silicon functional validation is the last "guardian" logic-wise before delivering the product to the market. In each CPU generation, the challenges are larger due to increasingly complex architectures, budget constraints and shorter schedules. Success can be achieved just with the novel approaches across different validation teams, and with a complex of state-of-the-art validation software, hardware, execution and silicon debug environments. Budget constraints lead to high automation and efficient validation process. Though Intel Corporation has different divisions, mutual help and hard work and optimization ensures high quality product within the schedule.
Date of Conference: 07-09 November 2007
Date Added to IEEE Xplore: 10 December 2007
Print ISBN:978-1-4244-1480-2
Print ISSN: 1552-6674
Conference Location: Irvine, CA, USA

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