Placement is one of the runtime bottlenecks in an EDA (Electronic Design Automation) tool flow. Detailed placement is an important part of placement which is hard to parallelize on a large scale. In this paper, we demonstrate GPU acceleration of a dynamic programming based detailed placement algorithm which solves a generalized version of the Linear Arrangement Problem. Although we test our algorithm on FPGA benchmarks, it can also be applied to ASIC placement [12]. Similar dynamic programming algorithms have also been used for simultaneous placement and routing [6]. To the best of our knowledge, this is the first reported GPU accelerated detailed placement algorithm other than simulated annealing. We achieve upto 7x speedup in runtime over multi-threaded CPU implementation without any loss of QoR.