In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question of how multiple signatures can be detected using the same set of pins. As a solution, we propose multiplexing techniques for power side channel communication, so that all watermarked cores inside the FPGA can be identified to establish a proof of authorship. We analyze different multiplexing methods in order to adapt them to power watermarking and provide experimental results with several cores concurrently transmitting signatures.