Abstract:
In this paper, a new state metric normalization technique is proposed for maximum-a-posteriori-probability (MAP) algorithm to enhance the throughput of MAP decoder. Bit-e...Show MoreMetadata
Abstract:
In this paper, a new state metric normalization technique is proposed for maximum-a-posteriori-probability (MAP) algorithm to enhance the throughput of MAP decoder. Bit-error-rate (BER) performance comparison showed that the MAP algorithm based on the proposed normalization technique has a coding gain of 0.25 dB at a BER of 10-4 in comparison with MAP algorithm based on the subtractive normalization technique. An architecture for MAP decoder based on the new normalization technique has been proposed with a reduced critical path delay as compared to the contributions in literature. Subsequently, a field-programmable-gate-array (FPGA) implementation of the new MAP decoder is carried out. Thereby, the proposed decoder based on non-parallel radix-2 and radix-4 architectures are able to achieve high throughputs of 514 Mbps and 1.028 Gbps respectively.
Published in: 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)
Date of Conference: 22-25 August 2013
Date Added to IEEE Xplore: 21 October 2013
ISBN Information: