Abstract:
This paper describes an integrated address sequencer for the Fast Fourier Transform. It also shows how this may be included in a high-speed signal processing peripheral.Metadata
Abstract:
This paper describes an integrated address sequencer for the Fast Fourier Transform. It also shows how this may be included in a high-speed signal processing peripheral.
Date of Conference: 03-05 May 1982
Date Added to IEEE Xplore: 29 January 2003