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Design framework for systolic-type arrays | IEEE Conference Publication | IEEE Xplore

Design framework for systolic-type arrays


Abstract:

We present a framework for the design and description of Systolic-type Arrays. The framework is based on the definition of a conceptual tool, Lines of Computation (LOC's)...Show More

Abstract:

We present a framework for the design and description of Systolic-type Arrays. The framework is based on the definition of a conceptual tool, Lines of Computation (LOC's) that allows us to systematically define a generalization of the idea of Systolic Arrays and Wavefront Array Processors. We use three different architectures for parallel matrix multiplication to show the power of LOC's to describe and generate Systolic-type Arrays. Finally, we present some topographical properties of Systolic Arrays that can be readily analyzed using LOC's ideas.
Date of Conference: 19-21 March 1984
Date Added to IEEE Xplore: 29 January 2003
Conference Location: San Diego, CA, USA

References

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