Pipelined cordic architectures for fast VLSI filtering and array processing | IEEE Conference Publication | IEEE Xplore

Pipelined cordic architectures for fast VLSI filtering and array processing


Abstract:

The paper presents a revised functional description of Volder's Coordinate Rotation Digital Computer algorithm (CORDIC), as well as allied VLSI implementable processor ar...Show More

Abstract:

The paper presents a revised functional description of Volder's Coordinate Rotation Digital Computer algorithm (CORDIC), as well as allied VLSI implementable processor architectures. Both pipelined and sequential structures are considered. In the general purpose or multi-function case, pipeline length (number of cycles), function evaluation time and accuracy are all independent of the various executable functions. High regularity and minimality of data-paths, simplicity of control circuits and enhancement of function evaluation speed are ensured, partly by mapping a unified set of micro-operations, and partly by invoking a natural encoding of the angle parameters. The approach benefits the execution speed in array configurations, since it will allow pipelining at the bit level, thereby providing fast VLSI implementations of certain algorithms exhibiting substantial structural pipelining or parallelism.
Date of Conference: 19-21 March 1984
Date Added to IEEE Xplore: 29 January 2003
Conference Location: San Diego, CA, USA

References

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