Loading [a11y]/accessibility-menu.js
Low Power Cordic IP Core Implementation | IEEE Conference Publication | IEEE Xplore

Low Power Cordic IP Core Implementation


Abstract:

There is a high demand for low power and efficient implementation of complex arithmetic operations in many Digital Signal Processing (DSP) algorithms. The CORDIC algorith...Show More

Abstract:

There is a high demand for low power and efficient implementation of complex arithmetic operations in many Digital Signal Processing (DSP) algorithms. The CORDIC algorithm is suitable to be implemented in DSP systems since its calculation for complex arithmetic is simple and elegant. However, the large number of iterations involved in CORDIC operation limits its speed performance seriously and also consumes large power. This paper presents three CORDIC IP cores which were implemented using a new CORDIC algorithm. Each of them has one of more distinctive performance in terms of power, area, speed and flexibility due to their different architectures.
Date of Conference: 14-19 May 2006
Date Added to IEEE Xplore: 24 July 2006
Print ISBN:1-4244-0469-X

ISSN Information:

Conference Location: Toulouse, France

References

References is not available for this document.