This paper presents a simulation environment, which is a C++/SystemC based integrated framework for functional verification of designed components or electronic architectures and enhances the existing computer architecture simulation tool named sefca. As the VHDL sources are converted to SystemC it is sufficient for verification engineers to have a fundamental knowledge of C++ and the SystemC library. The testbench framework uses the same graphical user interface (GUI) based on the wxPython library, which was presented in the sefca tool. Verification of the design is supported by the SystemC verification library (SCV). Inter-Process-Communication is used to send the stimuli for simulation input from the GUI to the simulation process and the simulation results back to the online viewer in the GUI. With these enhancements sefca becomes a universal tool for testing the software and the hardware part of a new design at the same time. Working on the transaction level model (TLM) the proposed methodology offers a high performance and a high level of abstraction.