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Energy optimization of LDPC decoder circuits with timing violations | IEEE Conference Publication | IEEE Xplore

Energy optimization of LDPC decoder circuits with timing violations

Publisher: IEEE

Abstract:

This paper presents a quasi-synchronous design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware comp...View more

Abstract:

This paper presents a quasi-synchronous design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. A quasi-synchronous low-density parity-check decoder processing circuit based on the offset min-sum algorithm is designed, achieving the same performance and occupying the same area as a conventional synchronous circuit, but using up to 28% less energy.
Date of Conference: 08-12 June 2015
Date Added to IEEE Xplore: 10 September 2015
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: London, UK

References

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