A yield improvement methodology using pre- and post-silicon statistical clock scheduling | IEEE Conference Publication | IEEE Xplore

A yield improvement methodology using pre- and post-silicon statistical clock scheduling


Abstract:

In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this p...Show More

Abstract:

In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper, we propose a comprehensive clock scheduling methodology that improves timing and yield through both pre-silicon clock scheduling and post-silicon clock tuning. First, an optimal clock scheduling algorithm has been developed to allocate the slack for each path according to its timing uncertainty. To balance the skew that can be caused by process variations, programmable delay elements are inserted at the clock inputs of a small set of flip-flops on the timing critical paths. A delay-fault testing scheme combined with linear programming is used to identify and eliminate timing violations in the manufactured chips. Experimental results show that our methodology achieves substantial yield improvement over a traditional clock scheduling algorithm in many of the ISCAS89 benchmark circuits, and obtain an average yield improvement of 13.6%.
Date of Conference: 07-11 November 2004
Date Added to IEEE Xplore: 31 January 2005
Print ISBN:0-7803-8702-3
Print ISSN: 1092-3152
Conference Location: San Jose, CA, USA

References

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