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Minimizing the number of test configurations for FPGAs | IEEE Conference Publication | IEEE Xplore

Minimizing the number of test configurations for FPGAs


Abstract:

FPGA test cost can be greatly reduced by minimizing the number of test configurations. A test technique is presented for FPGAs with multiplexer-based routing architecture...Show More

Abstract:

FPGA test cost can be greatly reduced by minimizing the number of test configurations. A test technique is presented for FPGAs with multiplexer-based routing architectures in which multiple logical paths through each multiplexer is enabled instead of only one path. It is shown that for Xilinx Virtex-II and Spartan-3 FPGAs only 8 test configurations are required to achieve 100% stuck-at, PIP stuck-on, and PIP stuck-off fault coverage.
Date of Conference: 07-11 November 2004
Date Added to IEEE Xplore: 31 January 2005
Print ISBN:0-7803-8702-3
Print ISSN: 1092-3152
Conference Location: San Jose, CA, USA

References

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